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timing generator for frame readout ccd image sensor description the CXD2470R is a timing generator ic which generates the timing pulses for performing frame readout using the icx224,icx284,icx202 and icx232 ccd image sensor. features base oscillation frequency 24.00 to 36.00mhz (max.) high-speed/low-speed shutter function supports quadruple-speed readout drive horizontal driver for ccd image sensor vertical driver for ccd image sensor applications digital still cameras structure silicon gate cmos ic applicable ccd image sensors icx224 (type 1/2, 2020k pixels) icx284 (type 1/2.7, 2020k pixels) icx202 (type 1/3, 1250k pixels) icx232 (type 1/3.6, 1250k pixels) pin configuration absolute maximum ratings supply voltage v dd v ss ?0.3 to +7.0 v v l ?0.0 to v ss v v h v l ?0.3 to +26.0 v input voltage v i v ss ?0.3 to v dd + 0.3 v output voltage v o1 v ss ?0.3 to v dd + 0.3 v v o2 v l ?0.3 to v ss + 0.3 v v o3 v l ?0.3 to v h + 0.3 v operating temperature topr ?0 to +75 ? storage temperature tstg ?5 to +150 ? recommended operating conditions supply voltage v dd b 3.0 to 5.5 v v dd a, v dd c, v dd d 3.0 to 3.6 v v m 0.0 v v h 14.5 to 15.5 v v l ?.0 to ?.0 v operating temperature topr ?0 to +75 ? ?1 e98y31c9z-ps sony reserves the right to change products and specifications without prior notice. this information does not convey any licens e by any implication or otherwise under any patents or other right. application circuits shown, if any, are typical examples illustr ating the operation of the devices. sony cannot assume responsibility for any problems arising out of the use of these circuits. CXD2470R 48 pin lqfp (plastic) * groups of pins enclosed in the figure indicate sections for which power supply separation is possible. 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 h2 v dd 3 v dd 4 xshp xshd xrs pblk clpdm v ss 4 obclp adclk v ss 5 cko cki osco osci v dd 5 mcko ssi sck sen vdi hdi v ss 6 h1 v ss 3 v ss 2 rg v dd 2 ebcksm v dd 1 wen id dsgat rst v ss 1 test2 sub v3b vl v3a v1b vh v1a v4 v2 vm test1
? 2 CXD2470R block diagram 3 2 3 7 4 8 3 5 3 4 3 9 4 4 4 3 4 1 5 4 2 4 2 3 2 2 2 0 1 9 2 1 1 8 1 7 1 6 1 5 1 0 9 8 1 1 1 3 1 2 1 4 2 8 2 7 2 6 2 5 3 0 7 2 9 1 v 1 b v 2 v 3 a v 1 a w e n i d v s s 5 a d c l k o b c l p c l p d m p b l k v s s 4 x r s x s h d x s h p v d d 4 v s s 2 r g v d d 2 v s s 3 h 2 h 1 v d d 3 v d i h d i t e s t 2 t e s t 1 r s t d s g a t v s s 1 3 6 v s s 6 v d d 5 v d d 1 m c k o c k o c k i o s c o o s c i p u l s e g e n e r a t o r 4 5 3 8 4 2 4 7 4 0 4 6 v l v m v h s u b v 4 v 3 b 3 1 3 2 3 3 s e n s c k s s i r e g i s t e r v d r i v e r 6 e b c k s m 1 / 2
? 3 CXD2470R pin description gnd internal system reset input. high: normal operation, low: reset control normally apply reset during power-on. schmitt trigger input/no protective diode on power supply side control input used to stop pulse generation. high: normal operation, low: stop control schmitt trigger input/no protective diode on power supply side vertical direction line identification pulse output. memory write timing pulse output. chksum enable. high: sum check invalid, low: sum check valid with pull-down resistor 3.3v power supply. (power supply for common logic block) 3.3v power supply. (power supply for rg) ccd reset gate pulse output. gnd gnd ccd horizontal register clock output. ccd horizontal register clock output. 3.3 to 5.0v power supply. (power supply for h1/h2) 3.3v power supply. (power supply for cds block) ccd precharge level sample-and-hold pulse output. ccd data level sample-and-hold pulse output. sample-and-hold pulse output for analog/digital conversion phase alignment. pulse output for horizontal and vertical blanking period pulse cleaning. ccd dummy signal clamp pulse output. gnd ccd optical black signal clamp pulse output. clock output for analog/digital conversion ic. logical phase adjustment possible using the serial interface data. gnd inverter output. inverter input. inverter output for oscillation. when not used, leave open or connect a capacitor. inverter input for oscillation. when not used, fix low. 3.3v power supply. (power supply for common logic block) system clock output for signal processing ic. 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 v ss 1 rst dsgat id wen ebcksm v dd 1 v dd 2 rg v ss 2 v ss 3 h1 h2 v dd 3 v dd 4 xshp xshd xrs pblk clpdm v ss 4 obclp adclk v ss 5 cko cki osco osci v dd 5 mcko i i o o i o o o o o o o o o o o i o i o pin no. symbol i/o description
? 4 CXD2470R serial interface data input for internal mode settings. schmitt trigger input/no protective diode on power supply side serial interface clock input for internal mode settings. schmitt trigger input/no protective diode on power supply side serial interface strobe input for internal mode settings. schmitt trigger input/no protective diode on power supply side vertical sync signal input. schmitt trigger input horizontal sync signal input. schmitt trigger input gnd ic test pin 1; normally fixed to gnd. with pull-down resistor gnd (gnd for vertical driver) ccd vertical register clock output. ccd vertical register clock output. ccd vertical register clock output. 15.0v power supply. (power supply for vertical driver) ccd vertical register clock output. ccd vertical register clock output. ?.5v power supply. (power supply for vertical driver) ccd vertical register clock output. ccd electronic shutter pulse output. ic test pin 2; normally fixed to gnd. with pull-down resistor 31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 ssi sck sen vdi hdi v ss 6 test1 vm v2 v4 v1a vh v1b v3a vl v3b sub test2 i i i i i i o o o o o o o i pin no. symbol i/o description
? 5 CXD2470R electrical characteristics dc characteristics (within the recommended operating conditions) v dd2 v dd3 v dd4 v dd1 , v dd5 rst, dsgat, ssi, sck, sen, ebcksm test1, test2 vdi, hdi h1, h2 rg xshp, xshd, xrs, pblk, obclp, clpdm, adclk cko, mcko v1a, v1b, v3a, v3b, v2, v4 sub v dd a v dd b v dd c v dd d v t+ v t v ih1 v il1 v ih2 v il2 v oh1 v ol1 v oh2 v ol2 v oh3 v ol3 v oh4 v ol4 i ol i om1 i om2 i oh i osl i osh 3.0 3.0 3.0 3.0 0.8v dd d 0.7v dd d 0.7v dd d v dd b ?0.8 v dd b ?0.8 v dd c ?0.8 v dd d ?0.8 10.0 5.0 5.4 3.3 3.3 3.3 3.3 3.6 5.5 3.6 3.6 0.2v dd d 0.3v dd d 0.3v dd d 0.4 0.4 0.4 0.4 ?.0 ?.2 ?.0 v v v v v v v v v v v v v v v v v v ma ma ma ma ma ma feed current where i oh = ?2.0ma pull-in current where i ol = 14.4ma feed current where i oh = ?.3ma pull-in current where i ol = 2.4ma feed current where i oh = ?.3ma pull-in current where i ol = 2.4ma feed current where i oh = ?0.4ma pull-in current where i ol = 7.2ma v1a/b, v2, v3a/b, v4 = ?.25v v1a/b, v2, v3a/b, v4 = ?.25v v1a/b, v3a/b = 0.25v v1a/b, v3a/b = 14.75v sub = ?.25v sub = 14.75v supply voltage 1 supply voltage 2 supply voltage 3 supply voltage 4 input voltage 1 * 1 input voltage 2 * 2 input voltage 3 output voltage 1 output voltage 2 output voltage 3 output voltage 4 output current 1 output current 2 item pins symbol conditions min. typ. max. unit * 1 these input pins are schmitt trigger inputs and do not have protective diodes on the internal power supply side. * 2 these input pins have internal pull-down resistors. note) the above table indicates the condition for 3.3v drive.
? 6 CXD2470R inverter i/o characteristics for oscillation (within the recommended operating conditions) item logical vth input voltage output voltage feedback resistor oscillation frequency pins osci osci osco osci, osco osci, osco symbol lvth v ih v il v oh v ol rfb f conditions feed current where i oh = ?.6ma pull-in current where i ol = 2.4ma v in = v dd d or v ss min. 0.7v dd d v dd d ?0.8 500k 20 typ. v dd d/2 2m max. 0.3v dd d 0.4 5m 50 unit v v v v v mhz item logical vth input voltage input amplitude pins cki symbol lvth v ih v il v in conditions fmax 50mhz sine wave min. 0.7v dd d 0.3 typ. v dd d/2 max. 0.3v dd d unit v v v vp-p item rise time fall time output noise voltage symbol ttlm ttmh ttlh ttml tthm tthl vclh vcll vcmh vcml conditions vl to vm vm to vh vl to vh vm to vl vh to vm vh to vl min. 200 200 30 200 200 30 typ. 350 350 60 350 350 60 max. 500 500 90 500 500 90 1.0 1.0 1.0 1.0 unit ns ns ns ns ns ns v v v v inverter input characteristics for base oscillation clock duty adjustment (within the recommended operating conditions) note) input voltage is the input voltage characteristics for direct input from an external source. input amplitude is the input amplitude characteristics in the case of input through a capacitor. switching characteristics (v h = 15.0v, v m = gnd, v l = ?.5v) notes) 1. the mos structure of this ic has a low tolerance for static electricity, so full care should be given for measures to prevent electrostatic discharge. 2. for noise and latch-up countermeasures, be sure to connect a by-pass capacitor (0.1 f or more) between each power supply pin (vh, vl) and gnd. 3. to protect the ccd image sensor, clamp the sub pin output at vh before input to the ccd image sensor.
? 7 CXD2470R switching waveforms v 1 a ( v 1 b , v 3 a , v 3 b ) v 2 ( v 4 ) s u b t t m h t t h m v h v m v l v m v l v h v l 9 0 % 1 0 % 9 0 % 1 0 % t t l m t t l m 9 0 % 1 0 % 9 0 % 1 0 % t t l h t t h l 9 0 % 9 0 % 1 0 % 1 0 % t t m l 9 0 % 1 0 % t t m l 9 0 % 1 0 % waveform noise v c m h v c m l v h v l v c l h v c l l
? 8 CXD2470R measurement circuit 1 2 3 4 5 6 7 8 9 1 0 1 1 1 2 1 3 1 4 1 5 1 6 1 7 1 8 1 9 2 0 2 1 2 2 2 3 2 4 2 5 2 6 2 7 2 8 2 9 3 0 3 1 3 2 3 3 3 4 3 5 3 6 3 7 3 8 3 9 4 0 4 1 4 2 4 3 4 4 4 5 4 6 4 7 4 8 v d i c k i c 6 c 6 c 6 c 6 c 6 c 6 c 6 c 6 c 6 c 5 c 5 c 4 c 3 c x d 2 4 7 0 r s e r i a l i n t e r f a c e d a t a h d i + 3 . 3 v 7 . 5 v + 1 5 . 0 v c 2 c 2 c 2 c 2 c 2 r 1 r 1 r 1 r 2 r 1 r 1 r 1 c 2 c 2 c 2 c 2 c 2 c 2 c 2 c 2 c 2 c 1 c 1 c 1 c 1 c 1 c 1 c 2 c1 3300pf c2 560pf c3 820pf c4 30pf c5 180pf c6 10pf r1 30 r2 10
? 9 CXD2470R ac characteristics ac characteristics between the serial interface clocks s s i 0 . 2 v d d d 0 . 2 v d d d 0 . 8 v d d d t s 2 t h 1 t s 1 t s 3 0 . 8 v d d d 0 . 8 v d d d s c k s e n s e n symbol t s1 t h1 t s2 t s3 definition ssi setup time, activated by the rising edge of sck ssi hold time, activated by the rising edge of sck sck setup time, activated by the rising edge of sen sen setup time, activated by the rising edge of sck min. typ. max. 20 20 80 20 unit ns ns ns ns serial interface clock internal loading characteristics (1) (within the recommended operating conditions) t h 1 e n l a r g e d v i e w e x a m p l e : d u r i n g f r a m e m o d e 0 . 2 v d d d t s 1 0 . 2 v d d d v 1 a v d i h d i h d i v 1 a s e n 0 . 8 v d d d symbol t s1 t h1 definition sen setup time, activated by the falling edge of hdi sen hold time, activated by the falling edge of hdi min. typ. max. 0 102 unit ns s * be sure to maintain a constantly high sen logic level near the falling edge of the hdi in the horizontal period during which v1a/b and v3a/b values take the ternary value and during that horizontal period. (within the recommended operating conditions)
? 10 CXD2470R serial interface clock output variation characteristics normally, the serial interface data is loaded to the CXD2470R at the timing shown in "serial interface clock internal loading characteristics (1)" above. however, one exception to this is when the data such as stb is loaded to the CXD2470R and controlled at the rising edge of sen. see "description of operation". 0 . 8 v d d d s e n o u t p u t s i g n a l t p d p u l s e symbol tpdpulse definition output signal delay, activated by the rising edge of sen min. typ. max. 100 5 unit ns (within the recommended operating conditions) serial interface clock internal loading characteristics (2) t h 1 e n l a r g e d v i e w 0 . 2 v d d d t s 1 0 . 2 v d d d v d i h d i v d i h d i s e n 0 . 8 v d d d e x a m p l e : d u r i n g f r a m e m o d e symbol t s1 t h1 definition sen setup time, activated by the falling edge of vdi sen hold time, activated by the falling edge of vdi min. typ. max. 0 200 unit ns ns * be sure to maintain a constantly high sen logic level near the falling edge of vdi. (within the recommended operating conditions)
? 11 CXD2470R r s t 0 . 2 v d d d t w 1 0 . 8 v d d d v d i , h d i m c k o t s 1 t h 1 0 . 2 v d d d 0 . 8 v d d d 0 . 2 v d d d rst loading characteristics symbol t w1 definition rst pulse width min. typ. max. 35 unit ns (within the recommended operating conditions) vdi and hdi loading characteristics symbol t s1 t h1 definition vdi and hdi setup time, activated by the rising edge of mcko vdi and hdi hold time, activated by the rising edge of mcko min. typ. max. 20 5 unit ns ns mcko load capacitance = 10pf * 1 (within the recommended operating conditions) d s g a t h 1 , h 2 , r g , x s h p , x s h d , x r s , a d c l k , p b l k , c l p d m , o b c l p t p d s g a t 0 . 2 v d d d 0 . 2 v d d d output timing characteristics using dsgat h1 and h2 load capacitance = 180pf, rg load capacitance = 30pf, xshp, xshd, xrs, pblk, clpdm, obclp and adclk load capacitance = 10pf (within the recommended operating conditions) symbol tpdsgat definition time until the above outputs go low after the fall of dsgat min. typ. max. 100 unit ns
? 12 CXD2470R 0 . 8 v d d d m c k o w e n , i d t p d 1 wen and id load capacitance = 10pf (within the recommended operating conditions) symbol tpd1 definition time until the above outputs change after the rise of mcko min. typ. max. 60 20 unit ns output variation characteristics
? 13 CXD2470R description of operation pulses output from the CXD2470R are controlled mainly by the rst and dsgat pins and by the serial interface data. the pin status table is shown below, and the details of serial interface control are described on the following pages. pin status table note) act means that the circuit is operating, and dis means that loading is stopped. l indicates a low output level, and h a high output level in the controlled status. also, vh, vm and vl indicate the voltage levels applied to vh (pin 42), vm (pin 38) and vl (pin 45), respectively, in the controlled status. pin no. 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 v ss 1 rst dsgat id wen ebcksm v dd 1 v dd 2 rg v ss 2 v ss 3 h1 h2 v dd 3 v dd 4 xshp xshd xrs pblk clpdm v ss 4 obclp adclk v ss 5 act act act act act act act act act act act act act act act act act l l act l l l l l l l l l l act act l l act l l l l l l l l l l act l act act act l l l l l l l l l l l act l l act act act act act act act h h h act 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 cko cki osco osci v dd 5 mcko ssi sck sen vdi hdi v ss 6 test1 vm v2 v4 v1a vh v1b v3a vl v3b sub test2 act act act act act act act act act act act act act act act act act act act act act act act act act act act vm vm vh vh vh vh vh l act act act l act act act act act vm vm vh vh vh vh vh act act act act act act act act act act vm vm vh vh vh vh vh act act act act act dis dis dis act act vm vl vm vm vl vl vl symbol cam slp stb dsgat rst pin no. symbol cam slp stb dsgat rst
? 14 CXD2470R serial interface control the CXD2470R basically loads and reflects the serial interface data sent in the following format in the readout portion at the falling edge of hdi. here, readout portion specifies the horizontal period during which v1a/b and v3a/b, etc. take the ternary value. note that some items reflect the serial interface data at the falling edge of vdi or the rising edge of sen. s s i s c k s e n 0 0 0 1 0 2 0 3 0 4 0 5 0 6 0 7 4 1 4 2 4 3 4 4 4 5 4 6 4 7 there are two categories of serial interface data: CXD2470R drive control data (hereafter "control data") and electronic shutter data (hereafter "shutter data"). the details of each data are described below.
? 15 CXD2470R control data data d00 to d07 d08 to d09 d10 to d11 d12 d13 to d14 d15 to d35 d36 to d37 d38 to d39 d40 to d47 symbol chip ctg mode ccd smd ldad stb cksm function chip enable category switching drive mode switching ccd switching electronic shutter mode switching adclk logic phase switching standby control check sum bit data = 0 data = 1 10000001 ? enabled other values ? disabled see d08 to d09 ctg. see d10 to d11 mode. icx224/icx284 icx202/icx232 see d13 to d14 smd. see d36 to d37 ldad. see d38 to d39 stb. see d40 to d47 cksm. rst all 0 all 0 all 0 0 all 0 all 0 1 0 all 0 all 0
? 16 CXD2470R shutter data data d00 to d07 d08 to d09 d10 to d17 d18 to d27 d28 to d35 d36 to d39 d40 to d47 symbol chip ctg svd shd spl cksm function chip enable category switching electronic shutter vertical period specification electronic shutter horizontal period specification high-speed shutter position specification check sum bit data = 0 data = 1 10000001 ? enabled other values ? disabled see d08 to d09 ctg. see d10 to d17 svd. see d18 to d27 shd. see d28 to d35 spl. see d40 to d47 cksm. rst all 0 all 0 all 0 all 0 all 0 all 0 all 0
? 17 CXD2470R detailed description of each data shared data: d08 to d09 ctg [category] of the data provided to the CXD2470R by the serial interface, the CXD2470R loads d10 and subsequent data to each data register as shown in the table below according to the combination of d08 and d09 . d09 0 0 1 1 d08 0 1 0 1 description of operation loading to control data register loading to shutter data register test mode d11 0 0 1 1 d10 0 1 0 1 description of operation quadruple-speed mode (default) frame mode (a field readout) frame mode (b field readout) frame mode note that the CXD2470R can apply these categories consecutively within the same vertical period. however, care should be taken as the data is overwritten if the same category is applied. shared data: d40 to d47 cksm [check sum] these are the check sum bits. apply the data shown below. this function is valid when ebcksm (pin 6) is low. msb lsb d07 d06 d05 d04 d03 d02 d01 d00 d15 d14 d13 d12 d11 d10 d09 d08 d23 d22 d21 d20 d19 d18 d17 d16 d31 d30 d29 d28 d27 d26 d25 d24 d39 d38 d37 d36 d35 d34 d33 d32 +) d47 d46 d45 d44 d43 d42 d41 d40 ? cksm 0 0 0 0 0 0 0 0 ? reflected when the total is "0". control data: d10 to d11 mode [drive mode] the CXD2470R drive mode can be switched as follows. however, the drive mode bits are loaded to the CXD2470R and reflected at the falling edge of vdi.
? 18 CXD2470R control data: d36 to d37 ldad [adclk logic phase adjustment] this indicates the adclk logic phase adjustment data. the default is 90 relative to mcko. control data: d38 to d39 stb [standby] the operating mode is switched as follows. however, the standby bits are loaded to the CXD2470R and control is applied immediately at the rising edge of sen. d37 0 0 1 1 d36 0 1 0 1 degree of adjustment ( ) 0 90 180 270 d39 x 0 1 d38 0 1 1 symbol cam slp stb operating mode normal operating mode sleep mode standby mode see the pin status table for the pin status in each mode. control data: d12 ccd [ccd switching] specifies ccd image sensor to be used. however, the ccd image sensor switching bit is loaded to the CXD2470R and reflected at the falling edge of vdi. the default is "icx224/icx284". d12 0 1 ccd icx224/icx284 icx202/icx232
? 19 CXD2470R control data/shutter data: [electronic shutter] the CXD2470R realizes various electronic shutter functions by using control data d13 to d14 smd and shutter data d10 to d17 svd, d18 to d27 shd and d28 to d35 spl. these functions are described in detail below. first, the various modes are shown below. these modes are switched using control data d13 to d14 smd. d14 0 0 1 1 d13 0 1 0 1 description of operation electronic shutter stopped mode high-speed/low-speed shutter mode htsg control mode the electronic shutter data is expressed as shown in the table below using d18 to d27 shd as an example. msb lsb d27 d26 d25 d24 d23 d22 d21 d20 d19 d18 0 1 1 1 1 0 0 c 0 0 1 1 3 ? shd is expressed as 1c3h . [electronic shutter stopped mode] during this mode, all shutter data items are invalid. sub is not output in this mode, so the shutter speed is the accumulation time for one field. [high-speed/low-speed shutter mode] during this mode, the shutter data items have the following meanings. the period during which svd and shd are specified together is the shutter speed. concretely, when specifying high-speed shutter, svd is set to "00h". (see the figure.) during low-speed shutter, or in other words when svd is set to "01h" or higher, the serial interface data is not loaded until this period is finished. the vertical period indicated here corresponds to one field in each drive mode. in addition, the number of horizontal periods applied to shd can be considered as (number of sub pulses ?1). note) the bit data definition area is assured in terms of the CXD2470R functions, and does not assure the ccd characteristics. symbol svd shd spl data d10 to d17 d18 to d27 d28 to d35 description number of vertical periods specification (00h svd ffh) number of horizontal periods specification (000h shd 3ffh) vertical period specification for high-speed shutter operation (00h spl ffh)
? 20 CXD2470R vdi shd 01 v1a sub wen smd 00h 02h svd 050h 10fh shd 01 svd v d i s p l s h d 0 1 v 1 a s u b w e n s m d 0 0 h 0 1 h s p l 0 0 h 0 2 h s v d 0 a 3 h 1 0 f h s h d 1 0 s v d further, spl can be used during this mode to specify the sub output at the desired vertical period during the low-speed shutter period. in the case below, sub is output based on shd at the spl vertical period out of (svd + 1) vertical periods. incidentally, spl is counted as "00h", "01h", "02h" and so on in conformance with svd. using this function it is possible to achieve smooth exposure time transitions when changing from low-speed shutter to high-speed shutter or vice-versa.
? 21 CXD2470R v d i v 1 a s u b w e n 0 1 1 1 e x p o s u r e t i m e 0 1 s m d v c k [htsg control mode] during this mode, all shutter data items are invalid. the v1a/b and v3a/b ternary level outputs are stopped, so the shutter speed is the value obtained by adding the shutter speed specified in the preceding vertical period to the vertical period during which these readout pulses are stopped as shown in the figure.
? 22 CXD2470R chart-1 vertical direction timing chart mode frame mode applicable ccd image sensor ?icx224/icx284 a f i e l d v d i h d i s u b v 1 a v 1 b v 2 v 3 a v 3 b v 4 c c d o u t 1 2 2 5 1 2 2 7 1 2 2 8 1 2 3 0 1 2 3 2 1 2 3 4 1 2 3 6 1 2 2 9 1 2 3 1 1 2 3 3 1 2 3 5 3 1 5 7 2 4 6 8 1 0 4 2 6 8 1 0 1 2 1 4 1 6 1 8 9 1 2 5 c c 3 1 1 2 4 b f i e l d 3 1 1 3 5 7 9 1 1 1 3 1 5 1 7 1 9 2 1 p b l k i d o b c l p c l p d m w e n 6 5 0 ( 1 3 0 0 ) 6 5 0 ( 6 5 1 ) a b * the number of sub pulses is determined by the serial interface. this chart shows the case where sub pulses are output in each h orizontal period. * id is low for lines where ccd out contains the r component, and high for lines where ccd out contains the b component.
? 23 CXD2470R chart-2 vertical direction timing chart mode quadruple-speed mode applicable ccd image sensor ?icx224/icx284 v d i h d i s u b v 1 a v 1 b v 2 v 3 a v 3 b v 4 c c d o u t 1 2 1 0 1 2 1 5 1 2 1 5 1 2 1 8 1 2 2 3 1 2 2 6 1 2 3 1 1 2 3 4 1 2 1 8 1 2 2 3 1 2 2 6 1 2 3 1 1 2 3 4 9 4 2 7 1 0 1 5 2 3 1 8 2 6 3 1 3 4 3 9 4 2 4 7 5 0 5 5 1 1 2 d d 1 6 1 1 2 1 6 9 4 2 7 1 0 1 5 1 8 2 3 2 6 3 1 3 4 3 9 4 2 4 7 5 0 5 5 5 8 p b l k i d o b c l p c l p d m w e n 3 2 5 3 2 5 * the number of sub pulses is determined by the serial interface. this chart shows the case where sub pulses are output in each h orizontal period. * id is low for lines where ccd out contains the r component, and high for lines where ccd out contains the b component.
? 24 CXD2470R chart-3 horizontal direction timing chart mode frame mode applicable ccd image sensor ?icx224/icx284 1 5 2 h d i m c k o h 1 h 2 v 1 a / b v 2 v 3 a / b v 4 s u b p b l k o b c l p c l p d m ( 1 8 4 8 ) 0 5 0 5 6 1 0 0 1 5 0 1 2 0 7 2 1 0 4 5 6 5 1 1 3 1 0 4 1 9 0 8 8 5 6 1 5 2 8 8 2 0 0 2 5 0 i d 1 0 4 w e n 2 1 4 1 8 8 2 1 4 1 6 8 1 3 6 * the hdi of this chart indicates the actual CXD2470R load timing. * the numbers at the output pulse transition points indicate the count at the mcko rise from the fall of hdi. * the hdi fall period should be between approximately 3.1 to 10.4 s (when the drive frequency is 18mhz). this chart shows a period of 115ck (6.4 s). * sub is output at the timing shown above when output is controlled by the serial interface data. * id and wen are output at the timing shown above at the position shown in chart-1.
? 25 CXD2470R chart-4 horizontal direction timing chart mode quadruple-speed mode applicable ccd image sensor ?icx224/icx284 1 5 2 1 6 8 1 3 6 1 0 4 7 2 1 6 8 1 3 6 1 0 4 7 2 h d i m c k o h 1 h 2 v 1 a / b v 2 v 3 a / b v 4 s u b p b l k o b c l p c l p d m ( 1 8 4 8 ) 0 5 0 5 6 1 0 0 1 5 0 1 2 0 1 2 0 1 5 2 8 8 5 6 5 6 5 1 1 3 1 0 4 1 9 0 8 8 5 6 1 5 2 8 8 2 0 0 2 5 0 i d 1 0 4 w e n 2 1 4 1 8 8 2 1 4 * the hdi of this chart indicates the actual CXD2470R load timing. * the numbers at the output pulse transition points indicate the count at the mcko rise from the fall of hdi. * the hdi fall period should be between approximately 3.1 to 10.4 s (when the drive frequency is 18mhz). this chart shows a period of 115ck (6.4 s). * sub is output at the timing shown above when output is controlled by the serial interface data. * id and wen are output at the timing shown above at the position shown in chart-2.
? 26 CXD2470R chart-5 horizontal direction timing chart (high-speed sweep: c) mode frame mode applicable ccd image sensor ?icx224/icx284 1 8 8 1 6 8 1 9 6 2 2 4 2 5 2 2 8 0 h d i m c k o h 1 h 2 v 1 a / b v 2 v 3 a / b v 4 s u b p b l k o b c l p c l p d m ( 1 8 4 8 ) 0 5 0 5 6 1 0 0 1 5 0 1 1 2 1 4 0 8 4 5 6 1 8 2 2 1 0 2 3 8 2 6 6 1 5 4 9 8 7 0 5 1 1 3 5 6 1 5 2 8 8 2 0 0 2 5 0 i d w e n 1 2 6 1 6 8 1 9 6 2 2 4 2 5 2 2 8 0 1 4 0 8 4 5 6 1 8 2 2 1 0 2 3 8 2 6 6 # 1 # 2 # 3 # 4 1 5 4 7 0 1 2 6 1 1 2 9 8 * the hdi of this chart indicates the actual CXD2470R load timing. * the numbers at the output pulse transition points indicate the count at the mcko rise from the fall of hdi. * the hdi fall period should be between approximately 3.1 to 10.4 s (when the drive frequency is 18mhz). this chart shows a period of 115ck (6.4 s). * sub is output at the timing shown above when output is controlled by the serial interface data. * high-speed sweep of v1a/b, v2, v3a/b and v4 is performed up to 22h of 1848ck (#758).
? 27 CXD2470R chart-6 horizontal direction timing chart mode frame mode applicable ccd image sensor ?icx224/icx284 h d i [ a f i e l d ] [ b f i e l d ] [ a ] [ b ] v 3 b v 4 v 3 b v 4 l o g i c a l i g n m e n t p o r t i o n v 1 a v 1 b v 2 v 3 a v 1 a v 1 b v 2 v 3 a ( 1 8 4 8 ) 0 5 6 7 2 1 2 0 8 8 1 3 6 1 0 4 1 5 2 1 8 4 2 0 0 1 6 8 2 1 6 ( 1 8 4 8 ) 0 5 6 7 2 1 2 0 8 8 1 3 6 1 0 4 1 5 2 1 6 8 1 0 7 1 1 0 9 1 1 1 7 5 1 0 2 9 1 0 2 7 1 1 3 3 1 1 3 1 * the hdi of this chart indicates the actual CXD2470R load timing. * the numbers at the output pulse transition points indicate the count at the mcko rise from the fall of hdi. * the hdi fall period should be between approximately 3.0 to 13.4 s (when the drive frequency is 18mhz). this chart shows a period of 115ck (6.4 s).
? 28 CXD2470R chart-7 horizontal direction timing chart mode quadruple-speed mode applicable ccd image sensor ?icx224/icx284 h d i [ d ] v 3 b v 4 v 1 a v 1 b v 2 v 3 a ( 1 8 4 8 ) 0 5 6 7 2 1 2 0 8 8 1 3 6 1 0 4 1 5 2 1 6 8 ( 1 8 4 8 ) 0 5 6 7 2 1 2 0 8 8 1 3 6 1 0 4 1 5 2 1 6 8 1 0 7 1 1 0 9 1 1 1 1 1 1 1 7 5 1 0 2 9 1 0 2 7 1 1 3 3 1 1 3 1 * the hdi of this chart indicates the actual CXD2470R load timing. * the numbers at the output pulse transition points indicate the count at the mcko rise from the fall of hdi. * the hdi fall period should be between approximately 3.1 to 10.4 s (when the drive frequency is 18mhz). this chart shows a period of 115ck (6.4 s).
? 29 CXD2470R chart-8 vertical direction timing chart mode frame mode applicable ccd image sensor ?icx/202/icx232 a f i e l d v d i h d i s u b v 1 a v 1 b v 2 v 3 a v 3 b v 4 c c d o u t 9 5 5 9 5 7 9 5 8 9 6 0 9 6 2 9 6 4 9 6 6 9 5 9 9 6 1 9 6 3 9 6 5 1 3 2 4 2 4 6 1 0 8 1 2 1 4 1 6 1 8 2 0 1 1 3 7 e g f g 4 0 1 3 6 b f i e l d 4 0 3 5 7 9 1 1 1 3 1 5 1 7 1 9 2 1 2 3 p b l k i d o b c l p c l p d m w e n 5 2 5 ( 1 0 5 0 ) 5 2 5 ( 5 2 6 ) * the number of sub pulses is determined by the serial interface data. this chart shows the case where sub pulses are output in e ach horizontal period. * id is low for lines where ccd out contains the r component, and high for lines where ccd out contains the b component.
? 30 CXD2470R chart-9 vertical direction timing chart mode quadruple-speed mode applicable ccd image sensor ?icx202/icx232 v d i h d i s u b v 1 a v 1 b v 2 v 3 a v 3 b v 4 c c d o u t 9 4 4 9 4 9 9 4 9 9 5 2 9 5 7 9 6 0 9 6 5 9 5 2 9 5 7 9 6 0 9 6 5 4 1 5 8 1 3 1 6 2 4 2 1 2 9 3 2 3 7 4 0 1 1 7 h h 2 0 1 1 7 2 0 1 4 5 8 1 3 1 6 2 1 2 4 2 9 3 2 3 7 4 0 4 5 p b l k i d o b c l p c l p d m w e n 2 6 2 2 6 2 * the number of sub pulses is determined by the serial interface data. this chart shows the case where sub pulses are output in e ach horizontal period. * id is low for lines where ccd out contains the r component, and high for lines where ccd out contains the b component.
? 31 CXD2470R chart-10 horizontal direction timing chart mode frame mode applicable ccd image sensor ?icx202/icx232 1 7 5 h d i m c k o h 1 h 2 v 1 a / b v 2 v 3 a / b v 4 s u b p b l k o b c l p c l p d m ( 1 5 6 0 ) 0 5 0 5 5 1 0 0 1 5 0 1 3 5 7 5 1 1 5 5 5 5 0 1 0 1 1 5 2 4 4 9 5 5 5 1 5 5 9 5 2 0 0 2 5 0 i d 1 1 5 w e n 2 7 0 2 4 2 2 7 0 1 9 5 1 5 5 * the hdi of this chart indicates the actual CXD2470R load timing. * the numbers at the output pulse transition points indicate the count at the mcko rise from the fall of hdi. * the hdi fall period should be between approximately 3.0 to 13.4 s (when the drive frequency is 18mhz). this chart shows a period of 115ck (6.4 s). * sub is output at the timing shown above when output is controlled by the serial interface data. * id and wen are output at the timing shown above at the position shown in chart-8.
? 32 CXD2470R chart-11 horizontal direction timing chart mode quadruple-speed mode applicable ccd image sensor ?icx202/icx232 1 7 5 1 9 5 1 5 5 1 1 5 7 5 1 9 5 1 5 5 1 1 5 7 5 h d i m c k o h 1 h 2 v 1 a / b v 2 v 3 a / b v 4 s u b p b l k o b c l p c l p d m ( 1 5 6 0 ) 0 5 0 5 5 1 0 0 1 5 0 1 3 5 1 3 5 1 7 5 9 5 5 5 5 5 5 0 1 0 1 1 5 2 4 4 9 5 5 5 1 5 5 9 5 2 0 0 2 5 0 i d 1 1 5 w e n 2 7 0 2 4 2 2 7 0 * the hdi of this chart indicates the actual CXD2470R load timing. * the numbers at the output pulse transition points indicate the count at the mcko rise from the fall of hdi. * the hdi fall period should be between approximately 3.0 to 13.4 s (when the drive frequency is 18mhz). this chart shows a period of 115ck (6.4 s). * sub is output at the timing shown above when output is controlled by the serial interface data. * id and wen are output at the timing shown above at the position shown in chart-9.
? 33 CXD2470R chart-12 horizontal direction timing chart (high-speed sweep: g) mode frame mode applicable ccd image sensor ?icx202/icx232 2 4 2 1 7 5 2 1 5 2 5 5 h d i m c k o h 1 h 2 v 1 a / b v 2 v 3 a / b v 4 s u b p b l k o b c l p c l p d m ( 1 5 6 0 ) 0 5 0 5 5 1 0 0 1 5 0 1 3 5 9 5 5 5 7 5 1 1 5 1 5 5 1 9 5 2 3 5 2 7 5 7 5 1 1 5 1 5 5 1 9 5 2 3 5 2 7 5 1 7 5 2 1 5 2 5 5 1 3 5 9 5 5 5 5 0 1 0 5 5 1 5 5 9 5 2 0 0 2 5 0 i d w e n # 1 # 2 # 3 * the hdi of this chart indicates the actual CXD2470R load timing. * the numbers at the output pulse transition points indicate the count at the mcko rise from the fall of hdi. * the hdi fall period should be between approximately 3.0 to 13.4 s (when the drive frequency is 18mhz). this chart shows a period of 115ck (6.4 s). * sub is output at the timing shown above when output is controlled by the serial interface data. * high-speed sweep of v1a/b, v2, v3a/b and v4 is performed up to 33h of 1295ck (#659).
? 34 CXD2470R chart-13 horizontal direction timing chart mode frame mode applicable ccd image sensor ?icx202/icx232 h d i [ a f i e l d ] [ b f i e l d ] [ e ] [ f ] v 3 b v 4 v 3 b v 4 v 1 a v 1 b v 2 v 3 a v 1 a v 1 b v 2 v 3 a ( 1 5 6 0 ) 0 5 5 7 5 1 3 5 9 5 1 5 5 1 1 5 1 7 5 1 9 5 ( 1 5 6 0 ) 0 5 5 7 5 1 3 5 9 5 1 5 5 1 1 5 1 7 5 1 9 5 8 4 3 9 0 3 9 2 3 9 8 3 * the hdi of this chart indicates the actual CXD2470R load timing. * the numbers at the output pulse transition points indicate the count at the mcko rise from the fall of hdi. * the hdi fall period should be between approximately 3.0 to 13.4 s (when the drive frequency is 18mhz). this chart shows a period of 115ck (6.4 s).
? 35 CXD2470R chart-14 horizontal direction timing chart mode quadruple-speed mode applicable ccd image sensor ?icx202/icx232 h d i [ h ] v 3 b v 4 v 1 a v 1 b v 2 v 3 a ( 1 5 6 0 ) 0 5 5 7 5 1 3 5 9 5 1 5 5 1 1 5 1 7 5 1 9 5 ( 1 5 6 0 ) 0 5 5 7 5 1 3 5 9 5 1 5 5 1 1 5 1 7 5 1 9 5 8 4 3 9 0 3 9 2 3 9 8 3 * the hdi of this chart indicates the actual CXD2470R load timing. * the numbers at the output pulse transition points indicate the count at the mcko rise from the fall of hdi. * the hdi fall period should be between approximately 3.0 to 13.4 s (when the drive frequency is 18mhz). this chart shows a period of 115ck (6.4 s).
? 36 CXD2470R chart-15 high-speed phase timing chart mode applicable ccd image sensor ?icx224/icx284/icx202/icx232 h d i h d i ' c k i c k o a d c l k m c k o h 1 h 2 r g x s h p x s h d x r s 5 5 / 5 6 1 8 8 / 2 4 2 1 * hdi' indicates the hdi which is the actual CXD2470R load timing. * the phase relationship of each pulse shows the logical position relationship. for the actual output waveform, a delay is added to each pulse. * the logical phase of adclk can be specified by the serial interface.
? 37 CXD2470R application circuit block diagram 2 6 2 7 3 7 4 8 3 1 3 2 3 4 3 5 3 0 2 5 2 3 2 2 2 0 1 9 1 8 1 7 1 6 m c k o v d i h d i c k o 1 0 d 0 t o 9 a d c l k o b c l p c l p d m p b l k x r s x s h d x s h p s c k 3 3 s e n s s i t e s t 2 t e s t 1 o s c o c k i 2 8 o s c i c c d o u t v - d r v r t d r v o u t v r b 6 3 2 5 4 e b c k s m d s g a t r s t w e n i d 1 2 1 3 9 r g h 2 h 1 4 1 4 3 3 9 v 2 v 1 b v 1 a 4 4 4 6 4 0 v 4 4 7 s u b v 3 b v 3 a c c d i c x 2 2 4 / i c x 2 8 4 i c x 2 0 2 / i c x 2 3 2 s / h c x a 2 0 0 6 q t g c x d 2 4 7 0 r a / d c x d 2 3 1 1 a r c o n t r o l l e r s i g n a l p r o c e s s o r b l o c k notes for power-on of the three ?.5v, +15.0v and +3.3v power supplies, be sure to start up the ?.5v and +15.0v power supplies in the following order to prevent the sub pin of the ccd image sensor from going to negative potential. t 1 t 2 1 5 . 0 v 0 v 7 . 5 v 2 0 % 2 0 % t 2 3 t 1 application circuits shown are typical examples illustrating the operation of the devices. sony cannot assume responsibility fo r any problems arising out of the use of these circuits or for any infringement of third party patent and other right due to same .
? 38 CXD2470R s o n y c o d e e i a j c o d e j e d e c c o d e p a c k a g e m a t e r i a l l e a d t r e a t m e n t l e a d m a t e r i a l p a c k a g e m a s s e p o x y r e s i n p l a t i n g 4 2 / c o p p e r a l l o y p a c k a g e s t r u c t u r e 4 8 p i n l q f p ( p l a s t i c ) 9 . 0 0 . 2 * 7 . 0 0 . 1 1 1 2 1 3 2 4 2 5 3 6 3 7 4 8 ( 0 . 2 2 ) 0 . 1 8 0 . 0 3 + 0 . 0 8 0 . 2 g l q f p - 4 8 p - l 0 1 l q f p 0 4 8 - p - 0 7 0 7 ( 8 . 0 ) 0 . 5 0 . 2 0 . 1 2 7 0 . 0 2 + 0 . 0 5 a 1 . 5 0 . 1 + 0 . 2 0 . 1 s o l d e r / p a l l a d i u m n o t e : d i m e n s i o n * d o e s n o t i n c l u d e m o l d p r o t r u s i o n . 0 . 1 0 . 1 0 . 5 0 . 2 0 t o 1 0 d e t a i l a 0 . 1 3 m 0 . 5 s s b d e t a i l b : s o l d e r ( 0 . 1 8 ) ( 0 . 1 2 7 ) d e t a i l b : p a l l a d i u m 0 . 1 2 7 0 . 0 4 0 . 1 8 0 . 0 3 + 0 . 0 8 0 . 1 2 7 0 . 0 2 + 0 . 0 5 0 . 1 8 0 . 0 3 package outline unit: mm

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